// HDB3整体系统模块

module HDB3proj (In_reset,
                 In_clock,
                 In_enable,
                 E1_clock,
                 V_code,
                 BV_code,
                 HDB3_code,
                 HDB3_wave,
                 Out_code);

    input  wire  In_reset,In_clock,In_enable;
    output wire Out_code;
    output wire E1_clock,V_code,BV_code;
    output wire [1:0] HDB3_code;
    output reg [1:0] HDB3_wave;

    wire PN_code;

    always @(*) begin
        case (HDB3_code)
            2'b01:HDB3_wave <= 2'b01;
            2'b10:HDB3_wave <= 2'b11;
            2'b00:HDB3_wave <= 2'b00;
            default: HDB3_wave <= 2'b00;
        endcase
    end

div50to2p048 diver (
    .clk_50(In_clock),
    .rst_n(In_reset),
    .clk_2p048(E1_clock)
);

random random(
    .clk(E1_clock),
    .rst_n(In_reset),
    .enable(In_enable),
    .out(PN_code)
);

HDB3_encoder encoder(
    .clk(E1_clock),
    .rst_n(In_reset),
    .code_out(HDB3_code),
    .code_in(PN_code),
    .V_code_TP(V_code),
    .BV_code_TP(BV_code)
);

HDB3_decoder decoder (
    .clk(E1_clock),
    .rst_n(In_reset),
    .in(HDB3_code),
    .out(Out_code)
);

endmodule //HDB3proj
